1. Field of the Invention
The invention relates generally to a method of manufacturing a transistor in a semiconductor device, and more particularly to, a method of manufacturing a transistor in a semiconductor device capable of improving a sheet resistance characteristic of a silicide layer formed on a gate electrode and the uniformity of the sheet resistance.
2. Description of the Prior Art
FIG. 1A through FIG. 1E are cross-sectional views of semiconductor devices for describing a method of manufacturing a transistor in the semiconductor device according to a prior art.
Referring now to FIG. 1A, a device isolation film 12 is formed at a device isolation region of a semiconductor substrate 11.
By reference to FIG. 1B, an ion implantation mask 13, by which a region where a device will be formed is opened, is formed. A well 14 is then formed at an exposed region of the semiconductor substrate 11 by means of an ion implantation process.
Referring now to FIG. 1C, a gate oxide film 15 and a polysilicon layer 16 are sequentially formed to have a given pattern on the well 14 by means of an oxidization process and deposition process. Next, a first LDD ion implantation layer 17 for forming a source/drain is formed by means of a low-concentration ion implantation process.
By reference to FIG. 1D, an impurity is injected into a lower region of edges of the LDD ion implantation layer 17 and the polysilicon layer 16 by means of the low-concentration ion implantation process having a given incident angle, thus forming a second LDD ion implantation layer 18.
Referring to FIG. 1E, a buffer oxide film 19 is formed at the sidewall of the polysilicon layer 16. Next, after an insulating film is formed on the entire structure, an insulating film spacer 20 is formed at the sidewalls of the gate oxide film 15 and the polysilicon layer 16 by means of an etch process. At this time, the insulating film on the polysilicon layer 16 and the first LDD ion implantation layer 17 is removed by the blanket etch process.
Thereafter, a high-concentration ion implantation layer 21, which is deeper than the first LDD ion implantation layer 17, is formed by means of a high-concentration ion implantation process using the polysilicon layer 17 and the insulating film spacer 20 as an ion implantation mask. Next, a source/drain 22 consisting of the high-concentration ion implantation layer 21 and the first and second LDD ion implantation layers 17 and 18 is formed by an activation annealing process. After a silicide layer 23 is formed on the source/drain 22 in order to reduce the contact resistance, the ion implantation mask 13 is removed. Thereby, a transistor is manufactured.
Generally, in a process of manufacturing a transistor having a design rule of below 0.2 μm the silicide layer 23 is formed using cobalt (Co). At this time, in case of forming the silicide layer 23 on a single crystal silicon substrate using Co like the source/drain 22, it is possible to secure a thermal stability even at a high temperature annealing process of over 850° C. On the contrary, in case of forming the silicide layer 23 on the polysilicon layer 16 using Co like the gate electrode, the silicide layer 23 is agglomerated and the grain of the polysilicon layer 16 is grown. Due to this, the sheet resistance (Rs) of the suicide layer 23 is degraded even in an annealing process of over 700° C. due to the line width of the gate electrode consisting of the polysilicon layer 16. In particular, there is a problem that the uniformity of the sheet resistance (Rs) is degraded depending on the region of the wafer. This problem further occurs when the grain of the polysilicon layer 16 is small.